The present invention relates to a circuit for storing information about modules. In particular, but not exclusively, the circuit stores information on modules connected to an interconnect such as a bus in an integrated circuit.
Integrated circuits are often provided with debug circuitry which allows the integrated circuit to be debugged. The integrated circuit usually comprises a bus and a plurality of modules connected to the bus which put packets onto the bus. The debug circuitry is one of these modules. The modules also usually include a CPU. In order to operate, the debug circuitry is arranged to receive information from an external tool, put that information onto the bus and to check the response to that information or to output the response to the external tool. The debug circuitry can also carry out internal checks within the integrated circuit.
However, these known circuits have a problem. If the external circuitry identifies that there is a problem with a module, it is difficult to identify what has caused the problem in that module. This is because the module issuing the information causing the difficulty will continue to put information onto the bus. This means that the information in the module may have significantly changed by the time that the module is looked at. This makes it difficult to ascertain why the module in question has caused the problem.
It is an aim of embodiments of the present invention to address the difficulties of the known arrangements.
According to one aspect of the present invention, there is provided in a system comprising an interconnect and a plurality of modules connected to the interconnect, a circuit for controlling which of said modules is able to put information onto said interconnect, said circuit comprising a store which stores status information for each module, said status information defining if the respective module is permitted to put information on said interconnect.
According to a second aspect of the present invention, there is provided a circuit comprising an interconnect; one or more modules connected to the interconnect; and circuitry for monitoring information put onto the interconnect by one or more modules, said circuitry comprising circuitry for determining if the information on the interconnect matches one or more conditions; and a store storing status information for each module, said status information defining for each module if the module is permitted to put information onto the interconnect, whereby a module is prevented from putting further information onto said interconnect if it is determined that information on the interconnect matches said one or more conditions.
According to a third aspect of the present invention, there is provided a circuit comprising an interconnect; one or more modules connected to the interconnect to put information onto the interconnect; an arbiter for determining which module is permitted to put information onto the interconnect; and a store comprising information for each module which defines if the module is permitted to put information onto said interconnect, said arbiter being connected to said store, wherein said arbiter only allows modules which have status information indicating that the module is permitted to put information onto the interconnect to win access to the interconnect.